How Scaleway brought the first RISC-V servers to the cloud

How Scaleway brought the first RISC-V servers to the cloud Build • Coline Seguret • 04/05/26 • 15 min read

In 2013, Scaleway was one of the first cloud providers to offer ARM bare metal instances — physical servers directly accessible without virtualization. Eleven years later, we did it again by launching the world’s first dedicated RISC-V server offering.

But how do you turn an ISA architecture into a fully operational cloud server? Here is a look behind the scenes of this industry first: from the instruction set itself to the hardware design choices that made it possible.

The rise of the RISC-V architecture

For decades, the processor world has been dominated by CISC (Complex Instruction Set Computing) architectures, with giants such as Intel and AMD shaping modern computing.

These architectures, designed to execute complex instructions with as few lines of code as possible, drove the development of laptops and servers. But with the rise of mobile phones in the 2000s, they proved less well suited, as they consumed more power and offered less flexibility for new use cases.

In response to these limitations, RISC (Reduced Instruction Set Computing) architectures, which had first emerged in the 1980s, made a strong comeback. Thanks to simpler instructions that processors can execute more quickly , they allow developers to optimize both energy consumption and performance.

ARM in particular helped bring RISC back into the mainstream for consumer applications, with lighter, more energy-efficient processors suited to smartphones and connected devices.

Today, RISC-V goes one step further by offering an open-source instruction set — the machine language understood by the processor. Unlike proprietary architectures such as x86 or ARM, this ISA (Instruction Set Architecture) is free and open to everyone, requires no licensing, and can be extended or modified freely.

Figure 1: CISC vs. RISC comparison table for a given core and task.

The RISC-V revolution and its impact

Launched in 2010 at the University of California, Berkeley, RISC-V builds on the legacy of earlier RISC architectures.

Its core principle is the modularity of the instruction set . Whereas previous generations (RISC I through IV) focused primarily on performance, RISC-V emphasizes flexibility. Designers can add extensions to tailor their processors to specific uses: vector computing, AI processing, encryption, and more.

While this approach makes it possible to design more specialized hardware, it also comes with drawbacks: every combination of extensions creates a new variant of the machine language . In other words, a program compiled for one configuration may not run on another. This fragmentation is now a concern for part of the community: Linus Torvalds , for example, has criticized the growing number of RISC-V variants .

To address this issue, the RISC-V Foundation introduced standardized profiles such as RVA23 , which define a common baseline of mandatory instructions and extensions that manufacturers must implement. These profiles give developers a stable foundation and ensure that the same software can run on different processors without recompilation.

When we say RISC-V is open source, it is important to distinguish between the ISA itself — the standard, which is open — and its physical implementation , which is not necessarily so. In most cases, the internal processor design and its development code ( HDL ) remain proprietary. Manufacturers therefore keep their trade secrets and business models while still following the public “grammar” imposed by the profile.

Without that shared baseline, the system would either have to emulate missing instructions — at the cost of extremely poor performance — or simply be unable to perform certain tasks that require specific hardware support, such as virtualization.

RISC-V is therefore at a turning point: balancing the promise of an open, customizable ISA with the challenge of maintaining a coherent and compatible ecosystem.

Figure 2:Composition of a RISC-V CPU ISA: Base ISA, Standard and Custom Extensions

The above diagram gives a sense of the “recipe” used to compose a RISC-V ISA: each letter corresponds to a standard or specialized extension that makes a given ISA unique. Take the SiFive U74, for example, used in the HiFive Unmatched development board.

Behind this ISA lies an “RV64GC (RV64IMAFDC),” which indicates a 64-bit architecture (RV64), with extensions for multiplication (M), atomic instructions (A), floating point (F and D), and compressed instructions (C). Who would have thought choosing a CPU could be this complex?

What challenges did Scaleway overcome to launch the first RISC-V Bare Metal offering?

Over the past few years, the RISC-V ecosystem has continued to grow and is being adopted more and more by industrial players. RISC-V is now supported by major projects such as Android and the Linux kernel , and it is even expected to be used in future NASA missions . The RISC-V Summit, the ecosystem’s flagship event, now brings together not only the historical founders and open-source community, but also cloud and semiconductor giants. It's a far cry from the early, low-profile conferences.

At Scaleway R&D, we had anticipated this momentum and set out to design the first cloud offering of RISC-V instances. But adapting the RISC-V hardware available at the time to the constraints of cloud computing turned out to be a real challenge .

Project genesis

Our goal was clear: launch the world’s first RISC-V Bare Metal offering. The challenge? Use boards that were not designed for datacenters and turn them into servers capable of powering the first RISC-V cloud offering.

Fortunately, Scaleway already had a complete infrastructure in place to provision Bare Metal servers. All that remained was to integrate this new architecture into our existing software environment.

Here is how that journey began, and how Scaleway is now contributing to the RISC-V revolution.

Identifying the right SoCs and manufacturers

The first step was to assess what hardware could actually be used. We began by identifying the key players, suppliers, and manufacturers. At the time, the options were limited, but two SoCs (systems on a chip) stood out:

TH1520, developed by T-Head (Alibaba Group’s semiconductor arm), powered by a Xuantie C910 processor.

JH7110, developed by StarFive Technology , powered by a SiFive U74 processor.

For performance reasons, we chose the TH1520.…