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microsoft/cheriot-kudu

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microsoft/cheriot-kudu

Description: cheriot-kudu is a 32-bit dual-issue RISC-V MCU core with CHERIoT support

Language: SystemVerilog

License: Apache-2.0

Stars: 7

Forks: 0

Open issues: 0

Created: 2025-08-14T21:54:29Z

Pushed: 2026-06-13T22:40:03Z

Default branch: main

Fork: no

Archived: no

README:

Project

This project welcomes contributions and suggestions. Most contributions require you to agree to a Contributor License Agreement (CLA) declaring that you have the right to, and actually do, grant us the rights to use your contribution. For details, visit https://cla.opensource.microsoft.com.

When you submit a pull request, a CLA bot will automatically determine whether you need to provide a CLA and decorate the PR appropriately (e.g., status check, comment). Simply follow the instructions provided by the bot. You will only need to do this once across all repos using our CLA.

This project has adopted the Microsoft Open Source Code of Conduct. For more information see the Code of Conduct FAQ or contact [opencode@microsoft.com](mailto:opencode@microsoft.com) with any additional questions or comments.

Trademarks

This project may contain trademarks or logos for projects, products, or services. Authorized use of Microsoft trademarks or logos is subject to and must follow Microsoft's Trademark & Brand Guidelines. Use of Microsoft trademarks or logos in modified versions of this project must not cause confusion or imply Microsoft sponsorship. Any use of third-party trademarks or logos are subject to those third-party's policies.

Introduction

cheriot-kudu is 32-bit RISC-V microcontroller currently under development at Microsoft. Feature highlights include

  • Configurable 4, 5 or 6 stage pipeline
  • in-order, dual-issue
  • RV32IMAC support
  • Bitmanip extension (zba, zbb, zbc, zbs)
  • CHERIoT support (same as cheriot-ibex)
  • Backward compatibility mode (same as cheriot-ibex)

See the following block diagram for an overview of cheriot-kudu hardwared design.

![image](doc/Kudu_block_diagram.svg)

Simulation and emulation

For VCS simulation, see the instructions in sim/ directory.

cheriot-safe provides an open-source FPGA platform for emulation and prototyping.

Notability

notability 3.0/10

Low-traction Microsoft repo, minimal stars.