microsoft/open-sinc

microsoft/open-sinc

Language: SystemVerilog

License: Apache-2.0

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Created: 2026-07-01T02:28:14Z

Pushed: 2026-07-01T05:48:19Z

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README: Copyright (c) Microsoft Corporation and contributors. All rights reserved.

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

SINC Hands-On Guide #

Trademarks This project may contain trademarks or logos for projects, products, or services. Authorized use of Microsoft trademarks or logos is subject to and must follow Microsoft’s Trademark & Brand Guidelines. Use of Microsoft trademarks or logos in modified versions of this project must not cause confusion or imply Microsoft sponsorship. Any use of third-party trademarks or logos are subject to those third-party’s policies.

Introduction ##

SInC (Secure Instruction Cache) is a hardware instruction cache that lets a security subsystem execute firmware images that are too large to fit in its on-chip instruction SRAM. A small local IRAM holds boot/critical code, and SInC transparently caches the rest of the instruction space — up to 16 MB — from external memory. Cache blocks stored externally are encrypted and authenticated so that integrity and confidentiality of the firmware image are preserved even when it lives off-die.

SInC is composed of two cooperating hardware blocks:

• Cache Interface Unit (CIU) — sits on the processor side of the cache. Owns the cache SRAM, tag/state, the 4-way set-associative lookup, and the FIFO replacement policy. Also enforces memory-protection attributes (via the integrated [MPU](src/mpu/)) on every fetch.
• Cache Management Unit (CMU) — services block misses by issuing AXI reads to external memory, decrypting and authenticating each block (AES-GCM / AES-XTS via the integrated [AES](src/aes/) core), and delivering the plaintext block to the CIU. The CMU also handles firmware-driven initialization commands (key install, image encrypt-on-load, address-translation programming, cache lockdown, performance counters, debug, etc.).

The block diagram, command set, register interface, and full programmer's model are documented in [docs/SInC_0100_AS.md](docs/SInC_0100_AS.md) (architecture) and [docs/sinc_0101_MAS.md](docs/sinc_0101_MAS.md) (micro-architecture). The verification plan lives in [docs/SInC_0100_UVM.md](docs/SInC_0100_UVM.md).

This repository contains the open-source RTL for SInC plus its sub-components (AES, MPU, AXI manager/subordinate, RAM wrapper with ECC, replaceable std-cell templates) and a set of C-based directed tests under [verif/c_tests/](verif/c_tests/). A UVM testbench will be added in a follow-up drop.

Tools Used ##

OS:

• Build instructions assume a Linux environment

Lint:

• Synopsys Spyglass
• Version X-2025.06-SP1-1
• Real Intent AscentLint
• Version 2019.A.p15 for RHEL 6.0-64, Rev 116515, Built On 12/18/2020

Simulation:

• Synopsys VCS with Verdi
• Version R-2020.12-SP2-7_Full64
• Verilator
• Version 5.044
• Mentor Graphics QVIP
• Version 2021.2.1 of AHB models
• Avery AXI VIP
• Version 2025.1 of axixactor
• ARM AXI Protocol Checker
• BP063-BU-01000-r0p1-00rel0 Axi4PC.sv must be acquired from the ARM website
• UVM installation
• Version 1.1d
• Mentor Graphics UVM-Frameworks
• 2022.3

Synthesis:

• Synopsys Fusion Compiler
• Version 2022.12-SP3

GCC:

• RISCV Toolchain for generating memory initialization files
• Version 2023.04.29
• riscv64-unknown-elf-gcc (g) 12.2.0
• G++ Used to compile Verilator objects and test firmware
• g++ (GCC) 11.2.0

CDC:

• Questa CDC
• 2023.4_3 5762808 linux_x86_64 29-Feb-2024

RDC:

• Real Intent Meridian
• 2022.A.P18.3

RDL Compiler:

• systemrdl-compiler==1.27.3
• peakrdl-systemrdl==0.3.0
• peakrdl-regblock==0.21.0
• peakrdl-uvm==2.3.0
• peakrdl-ipxact==3.4.3
• peakrdl-html==2.10.1
• peakrdl-cheader==1.0.0
• peakrdl==1.1.0

Other:

• Playbook (Microsoft Internal workflow management tool)

Repository Overview ##

open_sinc
├── CODE_OF_CONDUCT.md
├── CONTRIBUTING.md
├── LICENSE
├── Makefile
├── README.md
├── SECURITY.md
├── SUPPORT.md
├── config
│ └── all_boms.yml
├── docs
│ ├── sinc_0101_CTESTS.md # L3 C test plan
│ ├── sinc_0101_AS.md # Architecture Specification
│ ├── sinc_0101_UVM.md # Verification Plan
│ ├── sinc_0101_MAS.md # Micro-Architecture Specification
│ └── media/
├── src
│ ├── aes # AES core (incl. GF math, key expansion, modes)
│ ├── axi_mgr # AXI manager (master) interface
│ ├── axi_sub # AXI subordinate (slave) interface
│ ├── gp_aes # General-purpose AES wrapper
│ ├── mpu # Memory Protection Unit
│ ├── ram_wrapper # RAM wrapper (EDC/ECC, erase, RMW)
│ ├── sinc # SInC top-level + CMU / CIU / register block
│ │ ├── config
│ │ │ ├── bom.yml
│ │ │ ├── sinc_top.vf # Top-level Verilog filelist for sinc_top
│ │ │ ├── cdc/ # Questa CDC setup (waivers, constraints)
│ │ │ ├── lint/ # Spyglass / AscentLint setup
│ │ │ ├── rdc/ # Meridian RDC setup
│ │ │ └── synthesis/ # Fusion Compiler synthesis setup
│ │ ├── include/ # Shared `*.vh` / `*.svh` headers
│ │ ├── registers/ # SystemRDL register definitions
│ │ ├── upf/ # sinc upf file
│ │ └── rtl/ # SystemVerilog sources (sinc_top, CMU, CIU, ...)
│ └── std_cells # Replaceable std-cell templates (e.g. clock gate)
└── verif
└── c_tests # C-based firmware tests run by the embedded core

Each sub-component under src// follows the same internal layout:

src//
├── config/ # *.vf filelists and BOM metadata
├── include/ # *.vh / *.svh headers (if any)
└── rtl/ # SystemVerilog / Verilog sources

The top-level fileset for sinc_top lives at [src/sinc/config/sinc.vf](src/sinc/config/sinc.vf) and pulls in every block listed above.

Environment Variables ##

Required for build / lint / simulation:

COMPILE_ROOT: Absolute path to the root of this repository. The top-level Verilog filelist [src/sinc/config/sinc.vf](src/sinc/config/sinc.vf) and every per-block *.vf reference ${COMPILE_ROOT} to locate sources. The Makefile...